Microprocessor for SPPU 19 Course (SE - II - Comp. - 210254)
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Microprocessor for SPPU 19 Course (SE - II - Comp. - 210254) (Paperback, A. P. Godse, Dr. D. A. Godse)

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Microprocessor for SPPU 19 Course (SE - II - Comp. - 210254)  (Paperback, A. P. Godse, Dr. D. A. Godse)

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Highlights
  • Binding: Paperback
  • Publisher: Technical Publications
  • ISBN: 9788194799399
  • Edition: THIRD, 2024
  • Pages: 332
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  • Description
    Unit I Introduction to 80386 Brief History of Intel Processors, 80386 DX Features and Architecture, Programmers Model, Operating modes, Addressing modes and data types. Applications Instruction Set: Data Movement Instructions, Binary Arithmetic Instructions, Decimal Arithmetic Instructions, Logical Instructions, Control Transfer Instructions, String and Character Transfer Instructions, Instructions for Block Structured Language, Flag Control Instructions, Coprocessor Interface Instructions, Segment Register Instructions, Miscellaneous Instructions. (Chapters - 1, 2) Unit II Bus Cycles and System Architecture Initialization - Processor State after Reset. Functional pin Diagram, functionality of various pins, I/O Organization, Memory Organization (Memory banks), Basic memory read and writes cycles with timing diagram. Systems Architecture - Systems Registers (Systems flags, Memory Management registers, Control registers, Debug registers, Test registers), System Instructions. (Chapter - 3) Unit III Memory Management Global Descriptor Table, Local Descriptor Table, Interrupt Descriptor Table, GDTR, LDTR, IDTR. Formats of Descriptors and Selector, Segment Translation, Page Translation, Combining Segment and Page Translation. (Chapter - 4) Unit IV Protection Need of Protection, Overview of 80386DX Protection Mechanisms: Protection rings and levels, Privileged Instructions, Concept of DPL, CPL, RPL, EPL. Inter privilege level transfers using Call gates, Conforming code segment, Privilege levels and stacks. Page Level Protection, Combining Segment and Page Level Protection. (Chapter - 5) Unit V Multitasking and Virtual 8086 Mode Multitasking - Task State Segment, TSS Descriptor, Task Register, Task Gate Descriptor, Task Switching, Task Linking, Task Address Space. Virtual Mode - Features, Memory management in Virtual Mode, Entering and leaving Virtual mode. (Chapters - 6, 7) Unit VI Interrupts, Exceptions, and Introduction to Microcontrollers
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    Book Details
    Publication Year
    • 2024 January
    Table of Contents
    • Unit I Introduction to 80386 Unit II Bus Cycles and System Architecture Initialization Unit III Memory Management Unit IV Protection Unit V Multitasking and Virtual 8086 Mode Multitasking Unit VI Interrupts, Exceptions, and Introduction to Microcontrollers
    University Books Details
    Stream
    • Comp
    Degree/Diploma
    • Degree
    Additional Features
    Age Group
    • 18-52
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